What You Will Build
Application Runtime and Compute APIs
• Define and build the hardware abstraction layer (HAL) and compute API stack for ASHAI's RISC-V platform, including device discovery, memory management, kernel dispatch, and async execution
• Optimize the runtime for RISC-V vector (RVV 1.0) and AI accelerator extensions, exposing hardware capabilities through a clean and portable API surface
• Define the memory model for application workloads: unified address space, DMA, and large-allocation management for AI use cases
AI Framework Integration
• Own RISC-V backend development for leading AI inference frameworks: PyTorch, JAX, vLLM, TensorRT-LLM, llama.cpp, and Hugging Face Transformers
• Build the operator library and graph compiler integration that maps model graphs to ASHAI's AI accelerator and RISC-V vector units
• Drive performance benchmarking against GPU baselines: tokens per second, cost per token, and memory efficiency
Developer SDK and Toolchain
• Build the developer SDK: APIs, documentation, integration guides, and profiling tools that enable customers to onboard and optimize on ASHAI hardware
• Support the first hyperscale customer programs directly, providing embedded technical engagement from integration through production
• Own RISC-V toolchain integration: compiler support, ABI compatibility, and build system tooling for ASHAI-optimized binaries
System Architecture Collaboration
• Partner with the SoC Architecture team on hardware-software co-design: define the API contracts and programming model requirements that hardware must satisfy
• Partner with the System Software team to define the userspace ABI, driver contracts, and OS interface that the application platform depends on
• Represent the application developer perspective in architecture reviews, ensuring software requirements are first-class inputs to silicon decisions
What We Are Looking For
Required Experience
• 15+ years in systems software, runtime engineering, or developer platform engineering, with at least 5 years in senior technical leadership
• Hands-on experience building a compute runtime, hardware abstraction layer, or developer SDK for a novel or custom compute architecture
• Deep familiarity with AI/ML inference systems: model serving infrastructure, operator libraries, graph compilation, and the performance characteristics of large-model workloads
• Demonstrated ability to build and lead engineering teams across runtime, SDK, and developer tools disciplines
Strongly Preferred
• RISC-V architecture depth: ISA privilege levels, RVV vector extension, RISC-V toolchain (LLVM/GCC), and ABI conventions; experience contributing to or enabling the RISC-V software ecosystem is a strong signal
• Experience at a hyperscale cloud provider (AWS, Google, Meta, Microsoft, Oracle) in a custom silicon software or AI infrastructure role
• Background building ML framework backends or compute runtimes: CUDA, ROCm, OpenCL, Metal, or equivalent on non-standard hardware
• Prior experience taking a new hardware platform from zero to developer-ready: no existing ecosystem, no off-the-shelf toolchain
• Familiarity with confidential computing and its implications for the application layer: secure enclaves, attestation APIs, and confidential inference
Leadership Qualities
• Operates at both strategic and implementation levels: can define the platform architecture and contribute directly on critical-path components
• Developer empathy: understands what makes a platform compelling to adopt and what friction prevents it
• Strong communicator across technical and business audiences; able to engage directly with hyperscale customer engineering teams and represent the platform externally
• High tolerance for greenfield ambiguity: this role requires defining structure and priorities where none currently exist
Role Details
Reports To: Chief Technology Officer (CTO), with regular direct engagement with the CEO on product strategy and customer direction
Location: San Francisco Bay Area (preferred); hybrid considered for exceptional candidates