System Validation Engineer NCG 2026

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

About Astera Labs

Astera Labs is a rapidly growing semiconductor company redefining connectivity for AI and cloud infrastructure. Our intelligent connectivity solutions-built on PCIe, CXL, Ethernet, and custom fabrics-enable seamless data movement across compute, memory, and storage. As part of our team, you'll help validate the silicon that powers the world's most advanced AI platforms.

Role Overview

As an Entry-Level System Validation Engineer on the Taurus team, you will validate Astera Labs' Taurus Ethernet Smart Cable Modules and Taurus ASICs. You'll work on chip bring-up, system-level debug, and interoperability testing across real-world AI server and networking platforms, collaborating closely with electrical validation, firmware, and product applications teams.

Key Responsibilities

• Execute system validation test plans for Taurus Ethernet Smart Cable Modules.
• Perform chip bring-up and debug for Taurus ASICs in lab environments using oscilloscopes, protocol analyzers, BERTs, and network switches
• Validate high-speed interconnects and AI fabrics in custom silicon, including signal integrity, link training, FEC stats, and protocol compliance
• Collaborate with electrical validation, firmware, and product applications teams to root-cause issues and drive resolution
• Document validation results, debug findings, and contribute to bring-up notes and test reports

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• Strong academic foundation in circuit analysis, signals and systems, electromagnetics, or high‑speed digital design through coursework and labs
• Familiarity with PCIe, CXL, or Ethernet standards
• Familiarity with fundamental signal‑integrity concepts such as eye diagrams, jitter, noise, impedance, and transmission lines
• Exposure to electrical lab equipment (e.g., oscilloscopes, logic analyzers, network analyzers)
• Experience using scripting or programming languages such as Python, MATLAB, TCL, or C/C++
• Comfortable working with lab tools and debugging hardware
• Strong analytical and communication skills

Preferred Skills

• Exposure to post-silicon validation or bring-up of connectivity IP blocks
• Knowledge of signal integrity analysis and eye diagram interpretation
• Familiarity with Linux systems, shell scripting, and version control (Git)
• Understanding of AI workloads and how interconnect bandwidth impacts performance

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.