Staff Physical Design Engineer

Google LLC

Sunnyvale, CA

JOB DETAILS
SKILLS
ASIC (Application Specific Integrated Circuit), Alliance/Partner Management, Artificial Intelligence (AI), Artificial Intelligence (AI) Programming Languages, Cadence, Cloud Computing, Communication Skills, Computer Architecture, Computer Engineering, Computer Science, Cross-Functional, DFT (Design for Test), Electrical Engineering, Electricity, English Language, Equal Employment Opportunity (EEO), Feasibility Analysis, Federal Government, Floorplanning, Genetics, Government, IP (Internet Protocol), Integrated Circuit Packaging, Leadership, Mentoring, Network Architecture/Engineering, Network Operations Center, Operations Management, Operations Research, Optical Engineering, Optical Networking, Performance Tuning/Optimization, PerlScript Scripting Language, Place and Route, Product/Service Launch, Program Planning, Project Execution, Project/Program Management, Python Programming/Scripting Language, RTL Design, Recruiting/Staffing Agency, Regulatory Requirements, Reliability Engineering, Risk Management, Sales, Schedule Development, Security Architecture, Software Engineering, Supply Chain Management, Tcl-Tk, Technical Leadership, Technical Support, Technical/Engineering Design, Telecommunications, Timing Verification
LOCATION
Sunnyvale, CA
POSTED
30+ days ago

Staff Physical Design Engineer - Google Careers

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Staff Physical Design Engineer

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Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

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Minimum qualifications:

  • Bachelor"s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

  • 10 years of experience in physical design, with experience in leading the full-chip or complex subchip implementation (e.g., from RTL2GDSII, including key stages like floorplanning, place and route, and timing closure) of high-speed ASICs in process technologies.

  • Experience in Python, Tcl, or Perl scripting.

Preferred qualifications:

  • Master"s degree or PhD in electrical engineering, computer engineering, or computer science, with an emphasis on computer architecture.
  • Experience in technical leadership, managing execution schedules, mitigating risks, providing status updates, and driving cross-functional collaboration with internal teams and external vendors to improve flows.
  • Experience in Cadence Innovus, Synopsys DP, Mentor Calibre, STARRC, with a strong understanding of foundry technology files, rule decks, physical signoff, and 2.5D/3D IC packaging.
  • Strong understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
  • Excellent communication skills to articulate complex technical challenges and solutions.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google"s direct-to-consumer products. You"ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Staff Physical Design Engineer, you will lead the end-to-end physical design implementation of complex silicon projects. You will drive technical excellence from RTL to GDSII, oversee critical sign-off closures, and foster cross-functional collaboration to optimize power, performance, and area (PPA). Beyond project execution, you will serve as a technical leader, influencing methodologies, guiding vendor engagement, and ensuring predictable delivery through effective planning and communication.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $192,000-$278,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

  • Oversee the physical design implementation of complex blocks, subchips, and top-level designs, ensuring technical excellence and project success.

  • Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.

  • Partner with internal teams (RTL, DFT, methodology, package) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.

  • Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.

  • Own and plan the physical design execution schedule, actively communicating status and risks to management.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google"s Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google"s EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

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