Sr. Digital Verification Engineer Video Interface Products in Norcross Atlanta United States
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Sr. Digital Verification Engineer Video Interface Products
Location Norcross Atlanta United States
Date Posted Mar 9 2026
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Description
Synaptics is leading the charge in AI at the Edge bringing AI closer to end users and transforming how we engage with intelligent connected devices whether at home at work or on the move. As the go-to partner for the worlds most forward-thinking product innovators Synaptics powers the future with its cutting-edge Synaptics Astra AI-Native embedded compute Veros wireless connectivity and multimodal sensing solutions. Were making the digital experience smarter faster more intuitive secure and seamless. From touch display and biometrics to AI-driven wireless connectivity video vision audio speech and security processing Synaptics is the force behind the next generation of technology enhancing how we live work and play.
Overview
Synaptics is looking for a Sr. Digital Verification Engineer on the Video Interface Products team. This role offers a unique opportunity to perform all aspects of digital verification from test plan to tapeout in next-gen data and video connectivity ASICs. You will be responsible for test development coverage and debug across block and full-chip designs growing into a critical role alongside our design teams. This position reports to the Sr. Manager Digital Design Verification.
The typical base pay range for this position is USD 100000 - 157300 per year. Individual pay is determined by many factors including work location job-related skills experience and relevant education or training. This position is also eligible for a discretionary annual performance bonus equity and other benefits. Note that compensation listed in US role postings reflect the base salary only and do not include bonus equity or benefits.
Responsibilities & Competencies
Job Duties
Deliver detailed test plans for verification of interface designs by working with design engineers and architects and by reviewing specification documents
Create and enhance constrained-random verification environments using System Verilog and UVM
Identify and write all types of coverage measures for stimulus and corner-cases
Debug tests with design engineers to deliver functionally correct design blocks
Close coverage measures to identify verification holes and to enable high confidence tape-out.
Maintain and enhance DV flow setup
Support system validation and test teams for test vector generation and system bring up.
Use a methodical engineering approach to the analysis and diagnosis of complex technical issues or defects
Carry out verification tasks required to complete development work by developing a solid understanding of the system architecture and proposing changes and improvements where appropriate
Competencies
Strong proficiency in SystemVerilog and UVM
Understanding of industry-standard protocols such as USB AMBA and I3C
Proficiency in scripting languages including Python Perl or Tcl
Proficiency in C C for embedded CPU verification is desirable
Organized and creative thinker motivated and independent learner who can multitask in a dynamic environment able to create and implement new solutions where required
Expertise in UVM or equivalent System Verilog object-oriented verification methodology
Good understanding of assertion-based verification methodologies and familiarity with Formal Verification tools
Proactive self-starter able to work independently in a fast-paced environment
Well organized with strong attention to detail proactively ensures work is accurate
Positive attitude and work ethic unafraid to ask questions and explore new ideas Good design programming and problem-solving skills and able to solve problems through practical use of technology and a solid understanding of product architecture
Excellent communication skills and ability to collaborat