Qualifications & competencies:
• B.S. or M.S. in Physics, Materials Science, or Electrical Engineering
• Experience with the ATE tests systems, probers and test hardware. Experience with
testing memory is a plus (DRAM, FLASH, SRAM or any other emerging memory
technology).
• Proficient in data analysis tools like JMP and programming languages like Python or C.
• Demonstrated track record of product spec validation, reliability characterization, and
qualification.
• Strong communication skills and the ability to work both independently and in team
environment.
• Excellent analytical, organizational, and project management skills.
• Detail-oriented, organized approach to performing and reviewing work.
• Unquestionable ethics – treats people with respect; keeps commitments; inspires the
trust of others; works with integrity
• Commitment to our core values of Leadership, Innovation, Communication, Persistence,
Enthusiasm, and Respect
Physical Demands and Work Environment:
• Occasionally required to stand • Occasionally required to walk • Continually required to sit • Continually required to utilize hand and finger dexterity • Continually required to talk or hear • Continually utilize visual acuity to operate equipment, read technical information,
and/or use a keyboard • Occasionally required to lift/push/carry items less than 25 pounds.
Specific responsibilities will include:
• First silicon validation, debug, and qualification.
• Responsible for developing and implementing test plans, ATE test programs, silicon
validation, test methodology concepts, multi-site hardware development, product
characterization, and high-volume production support.
• Ability to lead teams and projects.
• Thrive working in a cross functional environment to define and execute product
characterization and validation plans.
• Knowledge of magnetic tunnel junction (MTJ) materials and devices is a plus.
• Ability to manage and communicate product qualification plans, timelines, status, and
results both internally and to external vendors.
• Technical point of contact with OEMs and customers
Headquartered in Chandler, Arizona, Everspin is the worldwide
leader in designing, manufacturing, and commercially shipping discrete and embedded
Magnetoresistive RAM (MRAM) into markets and applications where data persistence and
integrity, low latency, and security are paramount. With over 200 Million MRAM products
deployed in data center, cloud storage, energy, industrial, automotive, and transportation
markets, Everspin has built the strongest and fastest growing foundation of MRAM users in the world.
The Role
Reporting to VP Backend OPS, and based in our Chandler, Arizona headquarters, the SMTS
Product engineer is responsible for bringing all new MRAM products(NPI) to market involving
pre-Si design spec definitions; first Si verification; datasheet spec validation; developing wafer
sort, final test and characterization programs and reliability characterization. Responsibilities
include working with Design and Operations teams to create and execute characterization and
debug plans for circuit validation, screen development and debug of any non-conformance.
Additionally, the group works with the Process and Device teams to develop a yield pareto
correlating wafer sort and final test failure mechanisms to bit properties thus defining a path to yield improvement. In addition, during the qualification phase, group responsibilities involve reliability/technology certification (both standard JEDEC and technology specific stresses).