Senior SoC Design Engineer, Cloud

Google LLC

Sunnyvale, CA

JOB DETAILS
SKILLS
ASIC (Application Specific Integrated Circuit), ASIC Design, Analysis Skills, Artificial Intelligence (AI), Centers for Disease Control and Prevention (CDC), Cloud Applications, Cloud Computing, Computer Architecture, Computer Engineering, Computer Firmware, Computer Science, Computer Security, Construction, Construction Industry Software, Consulting, Cross-Functional, Debugging Skills, Design Flows, Design Verification, Digital Circuit Design, Documentation, Electrical Engineering, English Language, Equal Employment Opportunity (EEO), Genetics, German Language, Google Apps, Graphic Design, Industry Standards, Internet Security, Internet of Things, Network Operations Center, Operations Management, Operations Research, Operations Security (OPSEC), Perl Programming Language, Product Management, Project/Program Management, Python Programming/Scripting Language, RTL Design, Recruiting/Staffing Agency, Regulatory Requirements, Retail, Scripting (Scripting Languages), Simulation, Stock Purchase Plans, System-on-a-Chip (SoC), SystemVerilog, Tcl-Tk, Team Player, Technical Leadership, Technical Support, Technical/Engineering Design, Test Plan/Schedule, Testing, Validation Testing, Verilog Hardware Description Language
LOCATION
Sunnyvale, CA
POSTED
21 days ago

Senior SoC Design Engineer, Cloud - Google Careers

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Senior SoC Design Engineer, Cloud

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Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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Minimum qualifications:

  • Bachelor"s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of experience with RTL coding using Verilog/SystemVerilog.
  • Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
  • Experience with CDC, RDC, RTL Linting and LEC.

Preferred qualifications:

  • Master"s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with scripting languages (i.e. Tcl, Python or Perl).
  • Experience architecting RTL solutions employing software based construction, instantiation, customization and generation of RTL.
  • Experience with SOC implementation standards and interfaces (i.e. AXI).
  • Experience with CDC, RDC, RTL Linting and LEC.
  • Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google"s most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google"s TPU. You"ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

You will join a team working on SoC-level RTL design for our datacenter accelerators. In this role you will work on top-level RTL, architecture, design and implementation of global communication busses, and integration of complex ASIC designs. This is a highly cross-functional and central role that will require interactions with numerous ASIC development teams. You will own deliverables to the cross-functional teams (i.e. Physical Design, Verification, Validation, Firmware) at various project milestones. You will also be directly involved in defining and creating methodologies that enable a highly efficient design environment for all ASIC engineers.

In this role, you will be a key contributor to the development of Google"s AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. This position offers the opportunity to manage technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits

Learn more about benefits at Google.

Responsibilities

  • Write high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
  • Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
  • Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
  • Engage in CDC and RDC tool setup, analysis, triage and design changes.
  • Define and document the microarchitecture for complex digital designs within the TPU. Contribute to the development and enhancement of design tools, flows, and methodologies.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google"s Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google"s EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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