Senior Product Manager - Hardware

Efficient is developing the world's most energy-efficient general-purpose computer processor. Efficient's patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform's unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

The Hardware Product Manager defines the silicon product strategy and roadmap for Efficient Computer''s next-generation spatial computing platforms. This role sits at the intersection of architecture, silicon engineering, software, applications, and customer engagement by translating market and customer insight into actionable silicon product decisions. This role is responsible for ensuring that what gets built is the right thing to build: the right architecture decisions, the right customer tradeoffs, the right competitive positioning, and the right roadmap sequencing to drive design wins and long-term platform adoption. Defines product direction, market requirements, customer priorities, tradeoffs, and roadmap decisions. Engineering owns implementation and execution. This role determines what should be built and why and not how it gets built or when each task closes.

This role is best suited for candidates with strong product strategy, customer-facing, and technical decision-making experience rather than primarily project coordination or delivery management backgrounds. You will have significant influence on company strategy and product direction. It requires strong judgment under uncertainty, balancing long-term silicon and IP roadmap decisions against evolving customer and market requirements.

Success looks like:

• The silicon roadmap reflects real customer requirements and competitive insight
• Product specs are clear, complete, and signed off before tapeout with tradeoffs documented and owned
• Key customers can articulate why Efficient Computer''s silicon and IP are the right choices for their platform
• Architecture decisions are informed by market requirements
• Competitive benchmarking tells a consistent, credible story about Efficient Computer''s differentiation
• The Hardware PM is the person engineering, sales, and customers all go to for board, silicon and IP product direction

Key Responsibilities:

Silicon Product Strategy & Roadmap

• Define and own the silicon product roadmap, from near-term tape-out requirements to multi-generation platform strategy. Set priorities based on customer pull, competitive positioning, and architectural opportunity.
• Translate customer needs, market dynamics, and competitive insight into clear, actionable silicon product specifications that architecture and engineering teams can execute against.
• Own the Market Requirements Document (MRD) and product specification process. Ensure specs are complete, signed off, and updated as tradeoffs emerge, with tradeoffs and ownership explicitly documented.
• Partner with engineering to define performance targets, power envelopes, memory architecture, interface requirements, and feature prioritization for each product generation.
• Maintain a clear, current view of the silicon product portfolio: what exists, what''s in development, what''s planned, and how each generation maps to target markets and customer segments.
• Define product segmentation, SKU strategy, and feature packaging across silicon generations to align technical capabilities with target markets and business objectives.
• Own the IP strategy for silicon products in partnership with engineering and legal. Identify patentable innovations, prioritize IP development around key architectural differentiators, support licensing and ecosystem strategy, and maintain awareness of the competitive IP landscape.

Customer & Ecosystem Engagement

• Lead customer discovery and requirements-gathering for silicon and IP capabilities. Translate customer application requirements, power budgets, and deployment constraints into concrete silicon and IP product requirements.
• Represent Efficient''s silicon platform to customers, partners, and ecosystem participants. Own the product narrative in technical customer discussions, evaluation engagements, and design-win conversations.
• Define evaluation criteria and customer success metrics for silicon sampling and bring-up phases. Ensure customers have what they need to move from evaluation to production commitment.
• Partner with Applications Engineering to define the reference platform and software enablement requirements that allow customers to realistically evaluate Efficient silicon against their own workloads.
• Work with the SW PM to ensure silicon and IP roadmap decisions support a usable and scalable developer experience

Silicon Execution & Cross-Functional Leadership

• Drive alignment between product requirements and engineering execution priorities. Own the cross-functional product review process and ensure tradeoff decisions are made explicitly, documented, and communicated.
• Define and communicate tradeoff decisions to engineering. Provide clear product direction when tradeoff decisions are required.
• Partner with the Software PM on hardware-software co-design requirements, identifying where compiler, runtime, or SDK needs have silicon implications and driving alignment across both roadmaps.
• Maintain product documentation, specs, roadmap artifacts, and decision logs throughout the product lifecycle. Keep a living record of what was decided, why, and what changed.
• Support bring-up, validation, and customer sampling milestones by ensuring product requirements are clear and that evaluation success criteria are defined and agreed in advance.
• Partner with operations and manufacturing teams on productization readiness, lifecycle planning, and production ramp considerations.

Competitive & Market Intelligence

• Own competitive silicon analysis: benchmarking strategy, performance comparisons, and differentiation narrative. Understand the competitive landscape well enough to make roadmap calls.
• Define and communicate Efficient Computer''s silicon and IP differentiation story.
• Monitor the competitive landscape on a rolling basis. Surface emerging threats and opportunities to the roadmap before they become urgent. Adjust priorities when the market moves.
• Drive Efficient Computer''s participation in industry benchmarking and performance publication efforts. Ensure that public performance claims are accurate, reproducible, and positioned to win.

Evaluation Hardware & Developer Platforms

• Own the product roadmap for evaluation kits (EVKs), development boards, and reference modules. Define requirements, prioritize features, and manage tradeoffs between time-to-customer, cost, and capability.
• Translate customer evaluation workflows into EVK and board requirements. Ensure evaluation hardware enables the key use cases customers need to assess Efficient silicon.
• Partner with Marketing and Applications Engineering to define the full product scope for EVKs and boards: hardware interfaces, bundled firmware, software support packages, documentation, and out-of-box experience. Treat the EVK as a product, not an afterthought.
• Partner with hardware engineering, applications, and supply chain to bring EVK and module products to market on schedules that support customer engagement and sales pipeline timelines.
• Own pricing, positioning, and lifecycle decisions for evaluation hardware and module products. Define distribution approach and support commitments.
• Partner with operations and supply chain to manage component selection, manufacturability, lifecycle risk, and availability for EVK and module products.

Required Qualifications:

• 7+ years of experience in semiconductor product management, silicon architecture, or related technical leadership roles with direct ownership of product requirements, roadmap, and customer engagements
• Experience managing at least one full silicon product cycle from requirements definition through customer sampling, including spec ownership, tradeoff decisions, and post-silicon validation
• Working knowledge of SoC architecture concepts: memory hierarchy, power domains, on-chip interconnects, compute accelerators, and interface standards, sufficient to engage substantively with engineering teams
• Direct customer engagement experience: translating customer application requirements and deployment constraints into concrete silicon product requirements
• Ability to write MRDs, product specs, and feature requirements that engineering teams can build from without ambiguity and that remain accurate as tradeoffs evolve
• Strong cross-functional leadership across architecture, design, verification, software, and applications teams, with the ability to drive alignment and make decisions without always having formal authority
• Experience managing explicit tradeoffs between schedule, power, area, performance, and customer priority and communicating those decisions clearly to engineering and to customers
• Ability to establish credibility with silicon architects, hardware engineers, and technically sophisticated customers through clear thinking, genuine technical depth, and accurate product judgment

Preferred Qualifications

• Experience with MCUs, embedded AI processors, DSPs, FPGAs, spatial computing architectures, or dataflow accelerators
• Familiarity with embedded AI deployment workloads and edge inference application requirements, including power budgets, latency targets, and memory constraints
• Experience with silicon benchmarking methodology: designing benchmark suites, running reproducible comparisons, and publishing credible competitive results
• Background in competitive silicon analysis - including understanding of competing architectures, vendor positioning, and market segmentation in the edge AI or embedded compute space
• Experience with compiler-hardware co-design or hardware-software interface definition for novel compute architectures
• Familiarity with EDA flows, tapeout processes, and the product lifecycle from RTL through bring-up - sufficient to understand schedule and risk implications
• Experience in a startup environment with high ownership, incomplete information, and rapidly evolving product requirements

We offer a competitive salary for this role, generally ranging from $180,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Why Join Efficient?

Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.