Senior Design and Integration Engineer, Cloud TPU

Senior Design and Integration Engineer, Cloud TPU - Google Careers

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Senior Design and Integration Engineer, Cloud TPU

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Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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Minimum qualifications:

• Bachelor"s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in RTL design.
• Experience with digital design and microarchitecture design.
• Cross-functional experience with DV and PD teams.
• Experience in optimizing for performance, power, and area.

Preferred qualifications:

• Master"s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 10 years of RTL design experience.
• 4 years of experience in power optimization and experience with power analysis tools like PowerArtist and PTPX.
• Experience with Linting, CDC, RDC, LEC and experience with Scripting languages (i.e. Python or Perl).
• Experience optimizing RTL solutions, RTL design methodologies and automate front-end engineering flows.
• Experience in design automation, architecting RTL solutions and ASIC Synthesis flows.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google"s most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google"s TPU. You"ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Join the team designing and developing the On-Chip Network of Google"s next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. This role requires close collaboration with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver cutting-edge hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows.

As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google"s AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design to achieve timing, area, power, and manufacturability goals.
• Drive critical power optimization and automation initiatives across all on-chip-network components and subsystems.
• Support post-silicon validation and hardware debugging efforts to ensure successful deployment.
• Lead the development and enhancement of internal design tools, flows, and engineering methodologies.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google"s Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google"s EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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