Senior CMOS Test and Validation Lead, Analog Mixed-Signal, Raxium

Google LLC

Fremont, CA

JOB DETAILS
SKILLS
ASIC (Application Specific Integrated Circuit), ATE Testers, Accounts Receivable, Analog Signal, C++ Programming Language, CMOS, Cloud Computing, Computer Architecture, Computer Engineering, Computer Science, Construction, Consulting, Cost Control, DFT (Design for Test), Data Analysis, Data Collection, Debugging Skills, Electrical Engineering, English Language, Equal Employment Opportunity (EEO), Financial Services, Genetics, Integrated Circuit (IC) Design, Internet Security, Internet of Things, Laboratory, Laboratory Automation, Leadership, Mandarin Chinese Language, Manufacturing, Mechanical Engineering, Mentoring, Network Operations Center, Operations Security (OPSEC), Oscilloscope, PCB (Printed Circuit Board) Manufacturing, Product Engineering, Project/Program Management, Python Programming/Scripting Language, Quality Assurance Methodology, Recruiting/Staffing Agency, Regulatory Requirements, Requirements Management, Sales Closing Skills, Sales Management, Schematics, Semiconductors, Signal Integrity, Silicon Bringup, Spectrum Analyzers, Startup, Stock Purchase Plans, System Integration (SI), Technical Leadership, Test Automation, Test Design, Test Equipment, Test Program, Test Strategy, Testing, Validation Testing, Vendor/Supplier Management
LOCATION
Fremont, CA
POSTED
26 days ago

Senior CMOS Test and Validation Lead, Analog Mixed-Signal, Raxium - Google Careers

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Senior CMOS Test and Validation Lead, Analog Mixed-Signal, Raxium

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Minimum qualifications:

  • Bachelor"s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
  • 10 years of experience in Test Engineering and Post-Silicon Validation, with 5 years of experience in CMOS.
  • 2 years of experience in a technical leadership or lead architect role.
  • Experience with Analog Mixed-Signal Silicon.
  • Experience programming for lab automation and data analysis.

Preferred qualifications:

  • Master"s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with benchtop measurement equipment (High-bandwidth Oscilloscopes, Spectrum Analyzers, BERTs, VNAs).
  • Vendor management experience working with OSATs and PCB fabrication houses.
  • Familiarity with high-speed serial protocols (MIPI).
  • Proven track record developing C++/Python test code for automated test equipment.

About the job

As a Senior Test and Post-Silicon Validation Lead, you will drive the bring-up, characterization, and high-volume manufacturing (HVM) release of our next-generation Analog Mixed-Signal (AMS) ASICs. In this critical leadership role, you will bridge the gap between design, DFT, and product engineering, ensuring zero-defect quality and optimized cost-of-test for our upcoming product lines. You will architect ATE test strategies and guide a small team of engineers through complex yield and performance bottlenecks.

Google"s Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $334000 (USD) + 25% bonus target + bonus + equity + benefits

Learn more about benefits at Google.

Responsibilities

  • Lead and mentor a team of test and validation engineers through the entire post-silicon lifecycle, from first-silicon bench bring-up to ATE production release. Partner with IC Design and DFT teams during the pre-tapeout phase to define Post SIlicon Test Process and Design requirements.
  • Design, develop, and debug multi-site ATE test programs (Advantest V93000 or Teradyne UltraFLEX) focusing on high-efficiency parallel testing for digital and AMS blocks.
  • Drive exhaustive post-silicon validation across PVT corners. Ensure strict bench-to-ATE correlation for critical high-speed interfaces and analog blocks.
  • Oversee the architecture and schematic review of complex loadboards and probe cards, ensuring Signal Integrity and Power Integrity (SI/PI) standards are met for high-frequency measurements.
  • Automate data collection from wafer test.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google"s Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google"s EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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