| Location | San Francisco, CA |
Eridu in San Francisco, CA seeks an experienced ASIC verification lead to design and implement verification strategies for data‑center networking ASICs. You will drive gate‑level simulations, coverage analysis, and verification planning, collaborating with design and software teams.The role requires 8–15 years of hands‑on experience, a strong background in SystemVerilog/UVM, and expertise in Ethernet and PCIe protocols, with excellent communication to coordinate complex issues.#J-18808-Ljbffr