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Senior ASIC Physical Design Engineer - W2 Role - 100% Remote (US)

Saransh Inc

NULL, AK(remote)

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JOB DETAILS
SKILLS
ASIC (Application Specific Integrated Circuit), ASIC Design, ASIC Verification, Analysis Skills, Computer Engineering, Computer Systems, Customer Relations, DFT (Design for Test), DRC Flows, Datapath Design, Debugging Skills, Digital Circuit Design, Documentation, Electronic Design, Electronic Engineering, FPGA, Floorplanning, Functional Testing, IR (Infrared), IR Drop Analysis, Input/Output, LVS Flows, Low Power, Memory Hardware, Product Lifecycle, RTL Verification, Radio Engineering, Requirements Management, Support Documentation, System-on-a-Chip (SoC), Technical Presentation, Technical/Engineering Design, eCos
LOCATION
NULL, AK(remote)
POSTED
5 days ago
Role: Senior ASIC Physical Design Engineer
100% Remote (US)
Job Type: W2 Contract
Must Have: Experience taking a design through the full lifecycle on real hardware (FPGA, SoC, or ASIC)
About the Role:
You will join a digital hardware team and contribute across the full silicon development lifecycle - from preliminary analysis and micro-architecture definition through RTL development, functional verification, ASIC/FPGA/SoC implementation, on-hardware bring-up, and design documentation. Engineers are expected to be customer-facing: presenting technical solutions, gathering and documenting requirements, and supporting both PoC and production phases.
Responsibilities:
  • Own block- and chip-level physical implementation: floorplanning, placement, clock tree synthesis, routing, and ECO closure through sign-off
  • Close timing, power, and area (PPA) targets for high-performance compute subsystems: systolic arrays, compute tiles, memory macros, NoC, and I/O interfaces
  • Design and optimize power delivery networks (PDN), power grids, and IR-drop analysis; implement power gating, voltage domains, and multi-corner power integrity sign-off
  • Drive CTS and low-power implementation: skew/latency targets, clock gating integration, operand gating support, and DVFS-related timing corners
  • Run STA, EM/IR, DRC/LVS, and physical verification; manage multi-mode multi-corner (MMMC) constraints and synthesis-to-PnR handoff quality
  • Optimize floorplans for ML accelerator regularity: macro placement, datapath tiling, congestion management, and routability of high-utilization compute arrays
  • Collaborate with RTL, verification, DFT, and architecture teams on constraint definition, timing exceptions, ECOs, and post-silicon debug support
  • Support tape-out milestones on advanced nodes (7 nm, 5 nm, 3 nm or comparable): run management, QoR tracking, and foundry handoff
  • Strong problem-solving under schedule pressure, scripting (Tcl/Perl/Python), and fluency with industry flows (Innovus/ICC2, PrimeTime, StarRC, Calibre, RedHawk/Voltus)
Core Skills & Qualifications:
  • BSc/MSc in Electronics, Radio Engineering, Computer Engineering, or related field
  • Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals
  • Experience taking a design through the full lifecycle on real hardware (FPGA, SoC, or ASIC)

About the Company

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Saransh Inc