Senior ASIC Physical Design Engineer

Google LLC

Sunnyvale, CA

JOB DETAILS
SKILLS
ASIC Design, Android, Artificial Intelligence (AI), Automation Engineering, Cadence, Cloud Computing, Cloud Storage, Computer Engineering, Computer Science, Consumer Packaged Goods, Customer Service Management, DFT (Design for Test), Design Evaluation, Design Verification, Electrical Engineering, English Language, Equal Employment Opportunity (EEO), Field Sales, Financial Services, Floorplanning, Genetics, Graphic Design, Japanese Language, Manufacturing, Network Administration/Management, Network Operations Center, Operations Research, Options Analysis, Performance Tuning/Optimization, PerlScript Scripting Language, Place and Route, Problem Solving Skills, Product Design, Product Management, Product Support, Python Programming/Scripting Language, RTL Design, Recruiting/Staffing Agency, Regulatory Requirements, Reliability Engineering, Retail, Sales, Sales Management, Software Engineering, Static Analysis, Static Timing Tools, Stock Purchase Plans, Tcl-Tk, Technical Consulting, Technical/Engineering Design, Timing Verification
LOCATION
Sunnyvale, CA
POSTED
20 days ago

Senior ASIC Physical Design Engineer - Google Careers

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Senior ASIC Physical Design Engineer

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Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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Minimum qualifications:

  • Bachelor"s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

  • 7 years of experience with physical design (e.g. from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure).

  • Experience in Python, Tcl, or Perl scripting.

Preferred qualifications:

  • Experience working with external partners on Physical Design (PD) closure.

  • Experience in Static Timing Analysis (STA), with an understanding of how to define timing corners, margins and derates.

  • Experience with Synopsys/Cadence PnR tools.

  • Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.).

  • Understanding of DFT including Scan, MBIST and LBIST.

  • Understanding of performance, power and area (PPA) trade-offs.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google"s most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google"s TPU. You"ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an ASIC Physical Design Engineer, you will collaborate with RTL, Design for Testing (DFT), Floorplan, and full-chip Signoff teams. Additionally, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $237000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

  • Participate in the Physical Design of complex blocks.

  • Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS.

  • Collaborate with internal logic and internal and external teams to achieve the best Power/Performance Analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google"s Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google"s EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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