Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory.We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world.To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems.About the RoleBuild deep understanding of target workloads and characterize their compute, memory, bandwidth, and latency demands on a variety of target hardware platformsModel performance at every level — silicon, system, service, and end-to-end user experience — and connect insights across layersDevelop and maintain analytical and simulation-based models that project system performance across design and assumption variantsCollaborate with silicon, software, hardware, model, and service teams to align assumptions and deliver insightsValidate models against measured workload behavior and continuously improve fidelityTranslate findings into clear, actionable recommendations for architects, engineers, and leadershipProactively identify performance risks and design opportunities ahead of architectural commit pointsRequirements5+ years analyzing workload behavior and modeling system performance for consumer or data center productsBS in Computer Science, Electrical Engineering, or related technical disciplineHands-on experience with profiling, benchmarking, and tracing tools across the stackStrong programming skills in Python and at least one systems language (C/C++/Rust)Demonstrated ability to translate quantitative analysis into architectural recommendationsBonus QualificationsMS or PhD in a relevant technical disciplineExperience with hardware/software co-design and architectural exploration toolingFamiliarity with accelerator, SoC, or memory subsystem architectureComfort moving fluidly between rigorous quantitative work and cross-functional influenceCuriosity, technical depth, and a bias toward learning new system domains quicklyCompensationThe US base salary range for this full-time position is between $120,000 - $300,000 annually.The pay offered for this position may vary based on several individual factors, including job-related knowledge, skills, and experience. The total compensation package may also include additional components/benefits depending on the specific role. This information will be shared if an employment offer is extended.#J-18808-Ljbffr