Principal Product Application Engineer - Leo

Principal Product Application Engineer - LeoSan Jose, California, United StatesAstera Labs (NASDAQ: ALAB) provides rack‑scale AI infrastructure through purpose‑built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor‑based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end‑to‑end scale‑up, and scale‑out connectivity. The company's custom connectivity solutions business complements its standards‑based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .About the RoleAs a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer‑facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — owning firmware bring‑up, validation, and customer issue resolution from early silicon through production ramp.Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams.This position is required onsite in San Jose, CA.Key ResponsibilitiesLead firmware‑focused customer engagements for Leo CXL Smart Memory Controllers, including bring‑up support, feature enablement, and issue triage on customer platformsDevelop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystemsSpearhead internal and external discussions on design requirements of DDR4/DDR5 DRAM interfaces , including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuningServe as the primary firmware technical point of contact for key customer accounts (hyperscalers, OEMs), driving issue resolution and feature demonstrationsInterpret and implement requirements from CXL, PCIe, and JEDEC DDR specifications into robust firmware solutionsCollaborate with cross‑functional teams (FW engineering, HW, systems, product management) to deliver firmware releases and customer collateral on scheduleDevelop and maintain Python‑based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflowsContribute to technical documentation including application notes, release notes, design guides, and customer‑facing collateralRepresent the Leo team in customer technical reviews, design‑in engagements, and industry forumsBasic QualificationsBachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred8+ years of experience in firmware development, product applications engineering, or a related technical role supporting complex SoC/silicon products for Server, Storage, and/or Networking applicationsProfessional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidanceEntrepreneurial, open‑minded behavior and can‑do attitude — think and act fast with the customer in mind!Authorized to work in the US and available to start immediatelyRequired ExperienceHigh proficiency in C for embedded firmware development in RTOS environmentsWorking knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing conceptsProficiency in Python for scripting, test automation, and diagnostic toolingDeep hands‑on knowledge of high‑speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS featuresExperience with firmware bring‑up, debug, and validation of memory or I/O subsystems on server platformsStrong debugging skills with the ability to triage and root‑cause issues in complex embedded systemsFamiliarity with SoC interfaces including DDR controllers, PCIe controllers, and on‑chip memory subsystemsExperience working with developer workflows: SCM (preferably Git), code reviews, CI/CD pipelinesPreferred ExperienceExperience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI‑X, SR‑IOV, and error handlingHands‑on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipmentFamiliarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS conceptsExperience with server memory performance tuning — latency and bandwidth optimizationPrior customer‑facing or field applications experience in a semiconductor or systems company is a strong plusCompensationThe base salary range for this role is $1750,000 – $230,000 USD . Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.EEO StatementAstera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non‑binary people, veterans, parents, and individuals with disabilities.#J-18808-Ljbffr