Principal Mixed Signal Engineer – Texas Institute for ElectronicsHiring Department: Operational Services and StrategiesPosition Open To: All ApplicantsWeekly Scheduled Hours: 40Earliest Start Date: OngoingPosition Duration: Expected to ContinueLocation: AUSTIN, TXCompany OverviewTexas Institute for Electronics (TIE) is a transformative, well‑funded semiconductor foundry venture combining the agility of a startup with the scale of a national initiative.Our MissionA key part of our mission is to advance the state of the art in 3D heterogeneous integration (3DHI), chiplet‑based architectures and multi‑component microsystems—catalyzing breakthroughs across microelectronics, artificial intelligence, quantum computing, high‑performance computing and next‑generation healthcare devices.Our ImpactBacked by $1.4 billion in combined funding from DARPA, Texas state initiatives and strategic partners, we are building foundational capabilities in advanced packaging and integrated design infrastructure to restore U.S. leadership in microelectronics manufacturing.Our TechnologyTIE's 3DHI and chiplet integration platforms integrate novel thermal management and advanced interconnect solutions to deliver unprecedented performance and energy efficiency.BenefitsCompetitive health benefits (employee premiums covered at 100%, family premiums at 50%)Voluntary Vision, Dental, Life and Disability insurance optionsGenerous paid vacation, sick time and holidaysTeachers Retirement System of Texas, a defined benefit retirement plan, with 8.25% employer matching fundsAdditional voluntary retirement programs: Tax‑sheltered annuity 403(b) and deferred compensation program 457(b)Flexible spending account options for medical and childcare expensesRobust free training via LinkedIn Learning plus professional conference opportunitiesTuition assistanceExpansive employee discount program including athletic ticketsFree access to UT Austin libraries and museums with staff ID cardFree rides on all UT Shuttle and Austin CapMetro buses with staff ID cardPurposeThe purpose of the Principal Mixed Signals Engineer is to develop next‑generation digital subsystems and compute fabrics for 2.5D and 3D microsystems, enabling scalable high‑bandwidth integration across AI, HPC and wireless acceleration platforms.ResponsibilitiesDesign and develop high‑speed mixed‑signal I/O circuits for UCIe 2.5D and 3.0D die‑to‑die interfaces in 2.5D and 3D microsystems.Architect and optimize SerDes, clock/data recovery (CDR), equalization and transceiver circuits for high‑speed die‑to‑die and chip‑to‑chip links, including UCIe and PCIe physical layers.Collaborate with packaging, EDA and system modeling teams to co‑optimize mixed‑signal I/O performance across heterogeneous integration stacks.Lead silicon bring‑up, bench characterization and production testing of high‑speed I/O and mixed‑signal circuits—developing test methodologies, ATE programs and yield‑improvement strategies from prototype through volume production.Engage with industry partners and standards bodies (UCIe Consortium) to influence specification development.Mentor internal design teams on mixed‑signal design methodologies, high‑speed measurement techniques and production test best practices for multi‑die systems.Translate mixed‑signal design innovations into IP roadmaps and reference designs, driving alignment between research, productization and customer enablement for UCIe‑based chiplet ecosystems.Required QualificationsM.S. in Electrical Engineering with emphasis on analog/mixed‑signal or high‑speed circuit design (or equivalent practical experience).12+ years of experience in mixed‑signal or high‑speed I/O circuit design for SoC/ASIC, with direct involvement in SerDes, UCIe or comparable die‑to‑die/chip‑to‑chip interface IP.Deep expertise in high‑speed transceiver design—including TX/RX front‑ends, CDR, equalization (CTLE, DFE), PLLs/DLLs and signal‑integrity analysis for multi‑Gbps links.Hands‑on experience with silicon bring‑up, lab characterization (high‑speed oscilloscopes, BER testers, network analyzers) and production test development on ATE platforms.Proficiency with industry‑standard analog/mixed‑signal EDA tools (Cadence Virtuoso/Spectre, Synopsys HSPICE, Ansys HFSS/SIwave) and parasitic‑aware simulation methodologies.Strong cross‑disciplinary collaboration—able to interface with digital design, packaging, EDA and process engineering teams.Proven record of taking high‑speed mixed‑signal IP from design through silicon validation and into production.Location preference: Austin, TX. Hybrid arrangements possible with 30–50% travel.Preferred QualificationsPh.D. in Electrical Engineering with emphasis on analog/mixed‑signal or high‑speed circuit design (or equivalent practical experience).Direct design experience with UCIe 2.5D (single‑ended, shoreline‑optimized) and/or UCIe 3.0D (hybrid‑bonding, ultra‑short‑reach) physical‑layer implementations.Familiarity with heterogeneous integration challenges—including crosstalk modeling, power delivery network design and signal‑integrity in 2.5D/3D hybrid‑bonding and interposer stacks.Experience designing SerDes or high‑speed I/O IP at 28 Gbps and above (e.g., 56G/112G PAM4), with end‑to‑end ownership spanning specification, design, tape‑out, silicon characterization and production test.Knowledge of interconnect and chiplet standards (UCIe, BoW, CXL, PCIe Gen 5/6, NVLink, UALink) and their physical‑layer requirements and compliance testing.Track record of publications, patents, or industry leadership in mixed‑signal circuit design.Salary RangeTIE pays industry‑competitive salaries.Working ConditionsStandard office conditions.Repetitive use of a keyboard and mouse.Work ShiftMonday – Friday: Standard and flexible.Equal Opportunity EmployerThe University of Texas at Austin, as an equal opportunity/affirmative action employer, complies with all applicable federal and state laws regarding nondiscrimination and affirmative action. The University is committed to a policy of equal opportunity for all persons and does not discriminate on the basis of race, color, national origin, age, marital status, sex, sexual orientation, gender identity, gender expression, disability, religion or veteran status in employment, educational programs, activities and admissions.Pay TransparencyThe University of Texas at Austin will not discharge or in any other manner discriminate against employees or applicants because they have inquired about, discussed or disclosed their own pay or the pay of another employee or applicant. However, employees who have access to the compensation information of other employees or applicants as part of their essential job functions cannot disclose the pay of other employees or applicants to individuals who do not otherwise have access to compensation information, unless the disclosure is (a) in response to a formal complaint or charge, (b) in furtherance of an investigation, proceeding, hearing or action, including an investigation conducted by the employer, or (c) consistent with the contractor's legal duty to furnish information.Background ChecksA criminal history background check will be required for finalists under consideration for this position.Employment EligibilityRegular staff who have been employed in their current position for the last six continuous months are eligible for openings being recruited through University‑Wide or Open Recruiting.Retirement Plan EligibilityThe retirement plan for this position is Teacher Retirement System of Texas (TRS), subject to the position being at least 20 hours per week and at least 135 days in length. This position has the option to elect the Optional Retirement Program (ORP) instead of TRS, subject to the position being 40 hours per week and at least 135 days in length.Employment Eligibility VerificationIf hired, you will be required to complete the federal Employment Eligibility Verification I‑9 form and present acceptable documents within the third day of employment.E‑VerifyUniversity of Texas at Austin uses E‑Verify to check the work authorization of new hires effective May 2015. The university's company ID number for E‑Verify is 854197.E‑Verify Poster (English and Spanish) – PDFRight to Work Poster (English) – PDFRight to Work Poster (Spanish) – PDFComplianceEmployees may be required to report violations of law under Title IX and the Jeanne Clery Disclosure of Campus Security Policy and Crime Statistics Act (Clery Act).Employees who are identified as Campus Security Authority (Clery Act) will be notified and provided resources for reporting. Responsible employees under Title IX are defined and outlined in HOP‑3031. The Clery Act requires all prospective employees to be notified of the availability of the Annual Security and Fire Safety report. They may access the most recent report here or obtain a copy at University Compliance Services, 1616 Guadalupe Street, UTA 2.206, Austin, Texas 78701.#J-18808-Ljbffr