Principal Engineer, Hardware Application Engineering - Signal Integrity & Power Integrity

Principal Engineer, Hardware Application Engineering - Signal Integrity & Power Integrity

Location

Santa Clara, CA, US

Work Model:

Onsite (5 days per week)

Employment Type:

Permanent

Function:

Engineering / Architecture

Salary: $199,800-$266,400

About the Organization

The organization is a leading provider of semiconductor solutions that enable next-generation networking, connectivity, cloud infrastructure, and AI computing platforms. Its Customer Solutions Group works closely with some of the world's most demanding infrastructure customers, including hyperscale data centres, cloud service providers, and AI system developers.

The team acts as a technical bridge between silicon engineering teams, customers, and manufacturing partners, helping transform advanced semiconductor technologies into reliable, production-ready platforms. Engineers collaborate across hardware, software, and system disciplines to solve complex challenges from early architecture and design phases through large-scale deployment.

Role Overview

The organization is seeking a Principal Engineer specializing in Signal Integrity (SI) and Power Integrity (PI) to serve as a senior technical authority supporting high-performance networking and AI infrastructure platforms.

This role will focus on ensuring customer systems built on advanced silicon solutions meet the highest standards for performance, reliability, and production readiness. The engineer will lead SI/PI activities across the complete product lifecycle, including architecture definition, simulation, validation, compliance testing, customer enablement, and production ramp.

The position is a highly visible individual contributor role requiring deep technical expertise, strong customer engagement skills, and the ability to influence engineering teams across multiple disciplines.

Key Responsibilities

Serve as the senior SI/PI technical authority for customer platforms from early architecture through mass production.

Define and maintain high-speed layout, routing, stack-up, and power delivery guidelines.

Perform channel extraction, simulation, and design analysis for high-speed SerDes interfaces.

Provide recommendations to improve signal margins, performance, and system reliability.

Lead compliance testing and lab characterization, including BER/SER, eye diagrams, jitter, return loss, and crosstalk analysis.

Provide SerDes tuning guidance based on simulation results, lab measurements, and system data.

Perform power integrity analysis including PDN impedance, IR drop, transient response, decoupling effectiveness, and voltage droop.

Review customer and partner designs and provide SI/PI recommendations.

Collaborate with silicon, packaging, hardware, software, and operations teams to improve platform solutions.

Support reference platform development and validate SI/PI performance for new products.

Lead hands-on hardware debugging using advanced laboratory equipment such as VNAs, BERTs, oscilloscopes, TDR systems, and jitter measurement tools.

Develop technical training materials and deliver SI/PI best-practice sessions for customers and internal engineering teams.

Provide technical leadership for current and future high-speed SerDes technologies.

Represent the organization in customer discussions, technical reviews, and industry forums.

Required Qualifications

Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or related discipline.

15+ years of experience in hardware design, development, and validation of high-speed networking or computing systems.

10+ years of specialized experience in signal integrity and power integrity for high-speed SerDes platforms.

Strong expertise across the complete SI lifecycle:

Channel modelling and budgeting

PCB layout and stack-up definition

Post-layout extraction and simulation

Design optimization and troubleshooting

Compliance testing and tuning

Strong understanding of power integrity concepts including PDN modelling, impedance analysis, IR drop, and transient behaviour.

Experience with SI/PI simulation tools such as Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI, or equivalent.

Hands-on experience with high-speed validation equipment:

VNAs

BERTs

Real-time and sampling oscilloscopes

TDR systems

Jitter analysers

Proven experience supporting customer-facing engineering engagements.

Ability to communicate complex technical concepts to engineering teams and senior stakeholders.

Preferred Qualifications

Experience with Ethernet switching platforms, networking ASICs, or AI infrastructure systems.

Experience supporting large-scale data centre deployments.

Background in customer enablement and reference platform development.

Familiarity with ODM/CM design processes, qualification flows, and manufacturing requirements.

Experience with SerDes tuning methodologies and correlation between simulation, lab results, and field data.

Knowledge of chip-to-module, cable, connector, and high-speed interconnect ecosystems.

Demonstrated ability to influence product roadmaps through technical insights.

Leadership

Impact

In this role, you will:

Establish SI/PI technical standards for strategic customer engagements.

Drive production-quality hardware solutions for next-generation infrastructure platforms.

Act as a key technical partner between customers, engineering teams, and manufacturing partners.

Mentor engineers and promote best practices in high-speed hardware design.

Influence future product development through real-world system insights.

Represent the organization as a technical expert with customers and industry partners.