Physical Design Engineer

Job Details:

Job Description:

As a Physical Design Engineer, you will play a pivotal role in shaping the next generation of custom IP and SoC designs at Intel.

Your work will directly influence the cutting-edge technology that powers our products, driving advancements in performance, efficiency, and innovation. In this role, you will have the opportunity to engage in all aspects of physical design, from RTL to GDS, crafting a design database that is ready for manufacturing. Your expertise in optimizing designs for power, frequency, and area will contribute significantly to Intel's mission to deliver world-class technological solutions.

This is an exciting opportunity to be at the forefront of physical design engineering, working alongside industry experts to push the boundaries of what is possible in semiconductor technology.

Responsibilities will include but are not limited to:

• Perform physical design implementation of custom IP and SoC designs from RTL to GDS.
• Execute comprehensive physical design flows, including synthesis, floor planning, place and route, clock tree synthesis, static timing analysis, and power/clock distribution.
• Conduct verification and signoff activities such as formal equivalence verification, static timing analysis, power integrity analysis, and layout verification.
• Analyze results to identify and resolve violations related to timing, reliability, and design structure.
• Optimize designs for power, performance, and area using industry-standard EDA tools.
• Develop and refine physical design methodologies and flow automation to improve team efficiency and accuracy.
• Collaborate with teams to address design challenges and deliver robust solutions.

The ideal candidate should show the following behavioral traits:

• Strong communication skills, willing to work effectively in cross-functional teams.
• Enthusiasm for contributing to Intel's mission to deliver leading-edge technology and innovation.

Qualifications:

Minimum qualifications are required to be initially considered for this position.

• Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field, and 3+ years of experience in physical design;
• OR a Master's degree in Electrical Engineering, Computer Engineering, or a related field, and 2+ years of experience in physical design;
• OR a PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience listed above should be a combination of the following:
• In RTL-to-GDS implementation, including synthesis, place and route, and timing closure.
• In industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics for physical design tasks.
• In static timing analysis, floor planning, and power integrity analysis.
• Strong knowledge of low-power design techniques and methodologies.

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Demonstrated experience to solve complex design challenges through innovative and efficient solutions.
• Proven track record of disciplined execution and attention to detail in design implementation.
• Driving continuous improvement in design methodologies and automation.

We invite you to take the next step in your career by joining our team of talented engineers who are transforming the future of semiconductor technology.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Folsom

Additional Locations:

US, Texas, Austin

Business group:

The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel''s product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

• ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.