Senior PCIe Gen6/Gen7 Functional Post-Silicon Validation EngineerDuration: ContractExperience: 7+ YearsOverview We are seeking a highly motivated Senior PCIe Gen6/Gen7 Functional Post-Silicon Validation Engineer to lead validation of next-generation PCIe Switch and Retimer silicon.This role focuses on functional and protocol-level validation of Gen6/Gen7 devices, ensuring robust specification compliance by validating LTSSM behavior, link training, equalization flows, configuration space, data path integrity, and advanced error handling.You will collaborate closely with Architecture, Design, RTL, and Firmware teams to deliver high-quality silicon solutions.Responsibilities Lead post-silicon bring-up and functional validation of PCIe Gen6/Gen7 Switch and Retimer devicesDevelop and execute detailed functional validation test plansCover LTSSM transitions and link initialization sequencesVerify configuration space and capability structuresVerify flow control and credit managementValidate posted, non-posted, and completion TLP trafficVerify ASPM and L1 substatesSwitch Architecture Validate multi-port and multi-host switch configurationsValidate FLIT mode operationPAM4 functional behaviorEnhanced error containmentDebug LTSSM, link training, enumeration issuesDevelop Python automation frameworks and regression suitesWork with RTL and Firmware teams to root cause issuesDocument coverage and validation resultsRequired Qualifications Hands-on debugging of LTSSM failures, link training issues, transaction layer bugsExperience validating PCIe Switch or Retimer siliconDeep knowledge of TLP/DLLP, credit logic, replay buffersProfessional experience with Python automationPreferred Qualifications CXL protocol knowledgeCompliance workshop / interoperability event experience#J-18808-Ljbffr