Lead Design Engineer - DDR Validation & Insight Automation

Cadence in San Jose, California is seeking a skilled individual to lead electrical and functional validation for advanced DDR interfaces such as DDR5 and HBM4. The ideal candidate will create innovative testing strategies, transform data into insights, and drive collaborative debug processes.The role requires M. Tech + 4 years or B. Tech with 6 years of experience. The position offers a salary range of $114,800 to $213,200, along with benefits including paid vacation, 401(k), and a variety of medical plans.#J-18808-Ljbffr