Hardware Design Engineer

We are seeking a highly skilled ASIC Design / SDC Engineer to join a world-class silicon engineering team building next-generation networking chips for high-performance, web-scale, and service provider systems.The ideal candidate is a detail-oriented engineer who enjoys solving deep timing and constraint challenges, collaborating across disciplines, and driving silicon-level correctness from block to full chip.What You Will DoDevelop and maintain block-level and full-chip SDC constraints across functional and test modesDrive timing closure in collaboration with RTL, physical design, and DFT teamsDefine and validate constraints using industry-standard STA and constraint verification toolsAnalyze and resolve timing issues across complex multi-clock, multi-mode designsWork with architecture teams to understand clocking structures and timing intentReview and improve SDC quality, completeness, and correctness across blocks and full chipImprove methodologies for SDC reuse, propagation, and constraint automationSupport full-chip clocking strategy, diagrams, and documentationOptionally contribute to RTL design or IP integrationWhat You Bring4–6+ years (Master's) or 6+ years (Bachelor's) of ASIC / digital design experienceStrong expertise in SDC development and static timing analysis (STA)Deep understanding of clock domains and clock gatingDeep understanding of timing exceptions including false paths and multi-cycle pathsDeep understanding of asynchronous boundary handlingExperience with tools such as Synopsys Design Compiler, DCG, or Fusion CompilerExperience with tools such as PrimeTime or equivalent STA toolsStrong Verilog / SystemVerilog knowledgeProficiency in scripting languages, especially Tcl (required), Shell, and Perl (preferred)Experience working across block-level and full-chip timing closureNice to HaveExperience with timing constraint verification tools such as TCM or TimeVisionExposure to RTL design or microarchitectureBackground in high-performance networking, ASIC, or SoC developmentExperience improving EDA flows or design methodologiesIdeal CandidateThe ideal candidate is a detail-oriented engineer who enjoys solving deep timing and constraint challenges, collaborating across disciplines, and driving silicon-level correctness from block to full chip.#J-18808-Ljbffr