Graphics FE Integration Engineer

Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPU! You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural parameters, physical constraints, DFT logic and power intent. As a GPU Design Integration Engineer, you will be responsible for:

• RTL integration, assembly, partitioning, transformation and analysis.
• Package, qualify and deliver FE design collateral.
• Debug simulation failures and triage logic equivalence failures between designs.
• Ensure implementation readiness with RTL lint, custom checks, unit level synthesis and clock/reset/power domain crossing checks.
• Develop innovative methods to improve front-end design integration process.
• Author design integration specification documents.
• Review and signoff specifications for customers and IP providers.
• Collaborate effectively with Architecture, IP, DV, SOC, DFT, and IMPL teams spanning multiple sites.BS + 10 years of experience. Experience with Verilog/System Verilog. Experience with the one of the following scripting languages: Perl/Ruby/Python.Proficiency in logic design principles. Ability to analyze architectural and micro architectural details to drive design partitioning. Knowledge of PPA optimization techniques, Power Intent (UPF/CPF), CDC, RDC, synthesis, physical design and STA. Experience with RTL analysis and/or PPA optimization using Invio, LEC and Genus. Familiarity with GPU/CPU/SIMD Architecture and micro-architecture. Ability to work well in a team and be productive under aggressive schedules. Experience with scalable designs, design reuse, DFT insertion, LEC, Lint, codeline management, simulation and debugging tools. Ability to debug and solve various design integration issues in a timely manner. Ability to solve complex problems across multiple technical domains.