In this role, you will serve as the critical link between IP development and SoC integration. You will be responsible for defining and executing the qualification standards that ensure third-party and internal IPs are ready for high-performance silicon designs. Your day-to-day will involve developing automated front-end CAD flows, managing complex EDA tool collaterals, and collaborating with cross-functional teams to resolve technical integration bottlenecks. By streamlining the delivery process through advanced scripting and dashboarding, you will directly enable the team to hit aggressive tape-out schedules with high-quality, reliable silicon.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $163,000-$237,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.