Electrical/Optical SerDes Analog Mixed Signal Design Engineer

MediaTek Inc

  • Irvine, CA
  • 30+ days ago

    Highlights

    Design and verification of high-speed, high-performance analog and mixed-signal circuits including, but not limited to: modulator drivers (MRM/MZM/EAM), TIAs, front-end circuits, samplers, comparators, ADCs, DACs, PLLs, CDRs, clock distribution, heater drivers, and bias DACs. We are looking for ambitious analog and mixed-signal designers with exposure to silicon photonics and electro-optic systems who are willing to learn, grow, and contribute to a diverse portfolio of high-speed interconnect products.

    Numbers & Facts

    LocationIrvine, CA

    Description

    The Interconnect Solutions team is searching for qualified candidates to join our fast-growing team. As a member of this dynamic team, you will work on state-of-the-art next generation electrical and optical transceivers for data centers serving cloud infrastructure as well as the growing field of AI and high-performance computing. We are looking for ambitious analog and mixed-signal designers with exposure to silicon photonics and electro-optic systems who are willing to learn, grow, and contribute to a diverse portfolio of high-speed interconnect products.

    • Architecture study and evaluation of advanced high-speed SerDes and optical transceiver topologies targeting 100G/lane PAM4 and beyond, including EIC/PIC partitioning and link-budget definition.
    • Design and verification of high-speed, high-performance analog and mixed-signal circuits including, but not limited to: modulator drivers (MRM/MZM/EAM), TIAs, front-end circuits, samplers, comparators, ADCs, DACs, PLLs, CDRs, clock distribution, heater drivers, and bias DACs.
    • Electro-optic system modeling and co-simulation with PIC designs, including behavioural modeling of photonic devices (MRM, MZM, EAM, PD, heaters, laser sources) in Verilog-A, MATLAB, or Python.
    • Collaborate with package and SI/PI teams to define and sign off EIC-to-PIC interface, bump map, and supply distribution for co-packaged and advanced-packaging contexts.
    • Partner with DSP and algorithm teams on TX/RX equalization partitioning (analog CTLE/FFE/DFE vs. digital DSP) and link adaptation.
    • Evaluate, measure, and debug silicon with firmware and test teams through bring-up and post-silicon validation until it reaches high-volume production.

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