Contract Hardware Engineer Mid- #26-18015

US Tech Solutions, Inc.

  • San Jose, CA
  • Today

    Highlights

    US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. EDA exposure: Design compiler, PrimeTime, Tempus, Genus, Multi-Node Design: Experience working with 16nm, 7nm.

    Numbers & Facts

    LocationSan Jose, CA

    Description

    Duration: 12+ months
    Details:

    • Need Design Engineer with very strong experience Timing Constraints Writing. (this must reflect in resume)

    • RTL to Physical Design (RTL2PD) stage experience

    • RTL2PD Design Engineer (ASIC)

    MUST HAVE: RTL Synthesis, Constraint writing, validation, Static timing Analysis

    What candidate will Be Doing

    • RTL Synthesis, Constraint writing, validation, Static timing Analysis
    • Writing Scripts/Modifying scripts for RTL synthesis, SDC creation, STA
    • Debug synthesis issues and STA
    • Generate clean netlist.

    What we are looking for

    • Experience: 8–12 years of hands-on RTL Synthesis
    • EDA exposure: Design compiler, PrimeTime, Tempus, Genus,
    • Multi-Node Design: Experience working with 16nm, 7nm... etc nodes.

    About US Tech Solutions

    US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com.

    US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

    AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring.

    #LI-AS140

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