Design the next generation of USB solutions for Enterprise AI and IoT.
This position is for an analog layout designer to kickstart development for a new class of USB 2.0 and eUSB2 hubs, hosts, and bridges. Responsibilities include analog block-level layout, top-level floorplanning, I/O ring, power routing, DRCs, and GDSII handoffs for TI's advanced CMOS technologies.
Why TI?
+ Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.
+ We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI (https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/pages/4012)
+ Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us.
About Texas Instruments
Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com .
Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, disability, genetic information, national origin, gender, gender identity and expression, age, sexual orientation, marital status, veteran status, or any other characteristic protected by federal, state, or local laws.
If you are interested in this position, please apply to this requisition.
Minimum requirements:
+ Associates degree in Electrical Engineering Analog Layout
+ Analog layout experience with 65nm - 28nm CMOS process technologies
+ Proficient using Cadence tool flow.
+ Minimum of 5 years of experience
Preferred qualifications:
+ Bachelor's degree in Electrical Engineering
+ Prior experience in analog layout for USB or other relevant high-speed serial communication protocols (USB, PCIe, DisplayPort, Ethernet, etc.)
+ Top-level analog layout lead experience including floorplanning, power, ESD, I/O ring create
+ Working knowledge of chip-level reliability requirements and checks
+ Working knowledge of digital sub-chip integration
+ Ability to plan and track layout design activities
ECL/GTC Required: Yes