Silicon Design Verification Engineer (III)

Description

As a key contributor to a medium-sized project of moderate impact, you will be responsible for driving outcomes through verification execution, standards, and best practices. You will develop or enhance verification environments with foresight to anticipate and mitigate future issues. Typically, you will work on complex verification environments that require collaboration with a small team of engineers, such as a major functional block within an IP or projects of high verification complexity. You will share information and knowledge about Silicon Engineering technologies across teams with similar objectives. As a subject-matter specialist in Design Verification, you will utilize your comprehensive knowledge of Silicon engineering activities to deliver verified designs on schedule.

Responsibilities include:

• Developing test plans, including verification strategy, environment, components, stimulus, checks, and coverage, ensuring documentation is clear and accessible.
• Collaborating closely with architecture and design teams to verify the functional correctness of logic design.
• Working with cross-functional teams to debug failures, such as boards, software, manufacturing, design, and thermal issues, and providing quality solutions.
• Applying verification techniques and methodologies to drive design verification.
• Utilizing verification tools and languages, such as SystemVerilog, to drive design verification.

Minimum role qualifications require proficiency in:

• SV Coding Skills (10%)
• Simulation-based Verification Techniques, Methodology, and Experience (10%)
• Scripting and infrastructure (10%)
• Domain-specific knowledge (10%)
• Testbench components and techniques (10%)
• UVM Coding Skills (10%)
• SVA Coding Skills (10%)
• Python Scripting (10%)
• Formal Verification Techniques, Methodology, and Experience (10%)
• Communication and comprehension (10%)
• Problem-solving (10%)

For immediate consideration please click APPLY.