ASIC/RTL Design Engineer - Senior (US)

Lead micro-architecture definition and own end-to-end RTL design of SOC blocks, ensuring targets for functionality, timing, area, and power are met.

Develop and implement high-quality RTL in Verilog/SystemVerilog, including integration of ASIC IP into complex SOC environments.

Perform synthesis, static timing analysis (STA), timing optimization, and ensure clean Lint/CDC/RDC signoff.

Collaborate cross-functionally with architecture, verification, and physical design teams to drive successful tape-out.

Implement logic for testability, debug, and support silicon bring-up and post-silicon validation of owned features.

Develop automation and scripting solutions to improve design efficiency and contribute to clear technical documentation and design reviews.