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Design Verification Engineer job in Phoenix at Connexion Systems & Engineering

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Design Verification Engineer at Connexion Systems & Engineering

Design Verification Engineer

Connexion Systems & Engineering Phoenix, AZ Full-Time
$80.00 - $107.00/Hour
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*onsite work requires proof of vaccination, including booster shots.*

Key Qualifications
• Bachelor’s Degree in Electrical or Computer Engineering, or Computer Science
• 8+ years of experience verifying ASIC/FPGA devices
• Must have experience in developing HVL (System Verilog) based test environments, developing, and implementing test plans, implementing, and extracting verification metrics such as functional coverage.
• Expertise on verification methodologies such as VMM/OVM/UVM
• Must have strong written and oral communication skills and is able to demonstrate good analysis, debug, and problem-solving skills and self-driven.

  • Lead a verification team, mentor junior verification engineers
  • Integrate verification environment with design and complete verification to achieve closure
  • Summarize the verification and validation
  • Developing and executing product verification
  • Execute verification and validation procedures
  • Conduct design verification test activities through the development and maintenance of verification test plans, procedures and reports
  • Manage software verification and validation testing
  • Minimize issues in system verification and validation testing
  • Partake in verification environment architecture and methodology
  • Develop, maintain and publish verification specifications
  • Oversee design verification efforts of a cluster of blocks
  • Create the verification environment with scripts and makefiles
  • Support the definition and development of SSD ASIC verification strategies including appropriate state of the art verification techniques
  • Control the verification project environment including regression testing, verification tracking and configuration management
  • Develop tests and test bench components from high level verification plans
  • Generate design verification and stability project plans including planning for requirement verification, reliability and/ or stability activities
  • Report on progress toward completion of verification and validation
  • Architect, develop, maintain and enhance physical design verification (PDV)
  • Developing CPU verification and Testcode
  • Perform formal software development through design for requirements and requirements verification

Recommended Skills

  • Embedded Software
  • Firmware
  • Logic Synthesis
  • Systemverilog
  • Verilog
  • Vhsic Hardware Description Language (Vhdl)
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