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Aebb636bd7db226d5eba6025c561a578

Elect Design and Analy Engr

US Tech Solutions, Inc El Segundo, CA Contractor
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Job Description    

US Tech Solutions is seeking a “Elect Design and Analy Engr” for a 12 Months Contract with a client in El Segundo, CA

 

Job Poster: Sai Sharath

 

Job Description:

·        Utilize high-level architectural documentation along with algorithm descriptions to create self-checking and reusable testbenches from scratch

·        Develop Functional Coverage Models and Closing Code Coverage

·        Utilize UVM to create drivers, monitors, predictors, and scoreboards

 

Required Qualifications

·        Minimum of 14 years’ experience in Digital ASIC verification with at least 5 years focused on UVM

·        Experience with ASIC development including architectural definition, and detailed design implementation and functional verification using System Verilog.

·        Experience with design architecture and detailed specification generation.

 

Preferred Skills

·        Experience with UVMf

·        Experience with hardware emulators (Palladium, Veloce)

·        Proficiency with hardware verification languages: System Verilog, System Verilog Assertions

·        Ability to write executable test plans

·        Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.

·        Ability to create self-checking and reusable testbenches from scratch

·        Experience developing Functional Coverage Models and Closing Code Coverage

·        Proficient in scripting languages: Make, Perl, Python, etc.

·        Revision Control Systems: SVN, CVS, GIT

·        Proficient in Linux Environments

·        Demonstrated history of 1st pass success with ASIC designs.

 

Education:

·        Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience).

·        In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

 

About US Tech Solutions:

Your talent, our opportunities - This is the premise behind US Tech Solutions.

You have the skill we have the opportunity. As a team, we work passionately for you to get the right career opportunity across industry verticals and functions. For past sixteen years, leading Global

Companies and Fortune 500 come to us to get the right talent. Whether you want to work as full-time, contractor or part-time, technical or non-technical our talent consultants will connect with the right career opportunity globally.

Connect with our talent team today.

USTECH was founded in 2000 by Manoj Agarwal. Today, we are a global firm offering talent solutions to 150 customers including 20% of Fortune 500 across Financial Services, Healthcare, Life Sciences, Aerospace, Energy, Retail, Telecom, Technology, Manufacturing, and Engineering. We are headquartered in New Jersey with 40 global locations across the USA, Canada, Europe, and India. Deloitte has recognized USTECH as one of the fastest growing private businesses for the past five consecutive years and INC 500 for the past three. We have also been rated “The Top Business in the US" by Diversity Business since 2011. To learn more about how US Tech Solutions visit our website: www.ustechsolutions.com.

“US Tech is an Equal Opportunity Employer" and “US Citizens & all other parties authorized to work in the US are encouraged to apply."


Apply: Interested candidates are requested to send their resume to Sai at [ Email address blocked ] - Click here to apply to Elect Design and Analy Engr

Job Description    

US Tech Solutions is seeking a “Elect Design and Analy Engr” for a 12 Months Contract with a client in El Segundo, CA

 

Job Poster: Sai Sharath

 

Job Description:

·        Utilize high-level architectural documentation along with algorithm descriptions to create self-checking and reusable testbenches from scratch

·        Develop Functional Coverage Models and Closing Code Coverage

·        Utilize UVM to create drivers, monitors, predictors, and scoreboards

 

Required Qualifications

·        Minimum of 14 years’ experience in Digital ASIC verification with at least 5 years focused on UVM

·        Experience with ASIC development including architectural definition, and detailed design implementation and functional verification using System Verilog.

·        Experience with design architecture and detailed specification generation.

 

Preferred Skills

·        Experience with UVMf

·        Experience with hardware emulators (Palladium, Veloce)

·        Proficiency with hardware verification languages: System Verilog, System Verilog Assertions

Recommended skills

Git
Application Specific Integrated Curcuits
Mathematics
Concurrent Versions System (Software)
Physics
Perl (Programming Language)
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