Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) Design Engineer will be part of the core design team, responsible for the architecture, implementation, verification/validation through Software integration test, for delivery of complex FPGAs AND/OR ASICs systems.
S/he will develop architectures for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL, HLS) with high speed protocols– NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) AND/OR ASICs.
Additionally S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
We have deployed state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Client/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), Catapult (HLS).
This is a key, high impact, high visibility role in the organization to ensure robust quality and delivery of Communication products for National Security.
The successful candidate(s) will possess:
• At least 5 year experience with proven track record of implementing complex algorithms in networking ASIC/FPGAs
• Bachelor of Science in Electrical Engineering or Computer Science or equivalent
o Master of Science in Electrical Engineering or Computer Science preferred
• Proficiency in VHDL, C++ (OOP) and System Verilog Assertions (SVA)
• Experience with debugging in ARM ecosystem with Linux OS
• Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)
• Excellent Analytical/Debug skills
• Good verbal, written, and presentation skills
• US Government Secret security clearance or ability to obtain clearance required which includes US citizenship
A PLUS for prior experience with:
• High Level Synthesis (HLS) with Vivado, Mentor Catapult
• Xilinx MPSOC, and Vivado SDK and Linux super user
• Cryptographic and high speed networking designs
Nesco Resource and affiliates (Lehigh G.I.T Inc, and Callos Resource, LLC) is an equal employment opportunity employer and does not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, age, or veteran status, or any other legally protected characteristics with respect to employment opportunities.
Vhsic Hardware Description Language (Vhdl)
Field Programmable Gate Array
Application Specific Integrated Curcuits