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Wafer Level Packaging Research Integration Engineer at Intel

Wafer Level Packaging Research Integration Engineer

Intel Atlanta, GA Full-Time
**Job Description**

Join Intel and build a better tomorrow. Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us and help us create the next generation of technologies that will shape the future for decades to come.

**About the group:**

The Components Research Packaging and Systems Solutions group is a multidisciplinary team of researchers charged with developing novel technologies and package architectures to enable continued semiconductor scaling, mm-wave communications at various length scales and differentiating capabilities within packaging. There is a current need for a Wafer Level packaging integration engineer to focus on emerging 3D processes.

The Wafer Level Package Integration Research Engineer is responsible for partnering with process engineering, quality and reliability, and support teams to drive novel processes for both front end and back end 3D packaging integration.

Responsibilities may include, but are not limited to:

+ Initiating New Product Introductions and responding to quality events in the research and development process lines, containing, and dispositioning suspect material, and driving preventative measures.

+ Partner with process module engineers to drive novel, first of kind, integrated process flows.

+ Lead model-based problem-solving methodology to resolve process excursions.

+ Partner with Technology Development and AFO in research, development and future transfer of process technologies.

+ Develop strong partnerships beyond Components Research to Die Prep/Sort Process engineering and technology development teams.

The ideal candidate should exhibit the following behavioral traits:

+ Data analysis and problem solving skills.

+ Organizational skills with high attention to detail.

+ Interpersonal skills to work across diverse workgroups.

+ Communication and presentation skills.

+ Technical leadership skills.

We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.

**Minimum Qualifications:**

+ Ph.D. degree in Material Science, Chemistry, Chemical, Mechanical Engineering, or related field

+ 2+ years of wafer fab, die preparation, or assembly process experience

**Preferred Qualifications:**

+ Knowledge of statistical process control techniques, and JMP/SQL data analysis tools.

+ Knowledge of F/A tools such as SEM, EDX, etc.

+ Familiarity with fab automation systems such as MES and WS

**Inside this Business Group**

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

**Covid Statement**

Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.

**Posting Statement**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: [ Link removed ] - Click here to apply to Wafer Level Packaging Research Integration Engineer />
**Working Model**

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. **In certain circumstances the work model may change to accommodate business needs.**

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