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Located in Pasadena, California, JPL has a campus-like environment situated on 177 acres in the foothills of the San Gabriel Mountains and offers a work environment unlike any other: we inspire passion, foster innovation, build collaboration, and reward excellence.
We are seeking a **Digital Signal Processing Engineer IV** within the Telecommunications Signal Processing Engineering Group which is responsible for the design and implementation of the equipment that is used to track spacecraft missions within Deep Space Network. In this role you will lead a group of firmware, hardware, and software engineers in the development of communications signal processing systems for use in the Deep Space Network.
**What You Will Do:**
+ Lead the firmware/software design and development for highly complex signal processing applications through all phases of a project, from design, implementation, test, and deployment.
+ Lead the receiver and telemetry performance testing and functionality verification.
+ Update and maintain the existing Deep Space Network (DSN) digital receivers.
+ Provide engineering support to DSN Operations. Support spacecraft mission critical events and interface compatibility testing; monitor operational subsystem performance; assist DSN Operations with downlink performance issues and participate in subsystem troubleshooting.
+ Evaluate new or changed system requirements.
+ Develop and document subsystem and software requirements, design, and test procedures.
+ Review/update/maintain hardware and software interface agreements.
+ Prepare task cost estimates, schedules, and development plans.
+ Report on task progress to line and project management at Monthly Management Reviews.
+ Work with team to prepare and present materials at task design reviews and delivery reviews.
+ Work with line and project management to adjust plans to resolve issues as they arise.
+ Requires a Bachelor's degree in Electrical Engineering or similar discipline with a minimum of 9 years of related experience; or a Master's degree in a similar discipline with a minimum of 7 years of related experience; or a PhD in a similar discipline with a minimum of 5 years of related experience.
+ Minimum of 2 years of lead experience.
+ Demonstrated leadership experience of technical teams in the implementation of communications signal processing systems.
+ Strong theoretical background in modulation and demodulation schemes, telemetry encoding and decoding schemes (Viterbi, LDCP, turbo).
+ Practical experience in implementing hardware, firmware and software for signal processing systems that utilize high speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), and high-speed serial data links.
+ Experience testing and troubleshooting firmware/software implementations of signal processing systems.
+ Strong analytical and debugging skills.
+ Effective communication skills, both written and verbal.
+ Strong organizational and project management skills, including schedule and budget management.
+ Experience working closely with a team of software, firmware, and test engineers.
+ Demonstrated experience in leading the full lifecycle of ground system deployment from requirement definition, design, implementation, test, delivery, operations and maintenance.
+ Experience in preparing technical documentation including requirements documents, task plans, test documents.
+ Experience using git and github to manage a code base during development.
+ Demonstrated ability to explain complex issues to audiences with various levels of technical expertise.
+ Experience in developing firmware for FPGA based signal processing systems.
+ Knowledge or familiarity with Xilinx FPGAs and development tools and techniques such as Vivado.
+ Experience testing and troubleshooting complex firmware implementations using debug tools such as Xilinx ChipScope.
+ Knowledge and experience with MATLAB and Simulink simulations.
+ Experience in developing software in a Linux based development environment.
+ Working knowledge of C, C++, Python.
+ Experience with ethernet and related networking protocols, UDP, TCP/IP, etc.
+ Strong communication skills, interpersonal skills, and ability to manage projects on schedule and within allocated resources.
+ Ability to work on multiple projects in parallel.
JPL is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to sex, race, color, religion, national origin, citizenship, ancestry, age, marital status, physical or mental disability, medical condition, genetic information, pregnancy or perceived pregnancy, gender, gender identity, gender expression, sexual orientation, protected military or veteran status or any other characteristic or condition protected by Federal, state or local law.
In addition, JPL is a VEVRAA Federal Contractor.
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The Jet Propulsion Laboratory is a federal facility. Due to rules imposed by NASA, JPL will not accept applications from citizens of designated countries or those born in a designated country unless they are Legal Permanent Residents of the U.S or have other protected status under 8 U.S.C. 1324b(a)(3). The Designated Countries List is available here. ([ Link removed ] - Click here to apply to Digital Signal Processing Engineer IV
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