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FPGA Engineer
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FPGA:
Xilinx Vivado 2020.1 16 channel, 14-bit ADC, 2.50 GSPS XCZV49DR RfSoc development based on the ‘216’ dev board.
This is an unusual and relatively simple implementation of a direct conversion receiver below 100 MHz.
FPGA:
Xilinx Vivado 2020.1 16 channel, 14-bit ADC, 2.50 GSPS XCZV49DR RfSoc development based on the ‘216’ dev board.
This is an unusual and relatively simple implementation of a direct conversion receiver below 100 MHz.
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