Senior Engineer Package Designer

The PJF Group

San Jose Bay Area, CA

JOB DETAILS
SKILLS
ASIC (Application Specific Integrated Circuit), Analysis Skills, Bit Error Rate (BER), Communication Skills, Cross-Functional, Ethernet, HFSS (High Frequency Structure Simulator), HSPICE, IP (Internet Protocol), Marketing, PCI Express (PCI-E), Post-Sales, Presentation/Verbal Skills, Printed Circuit Board Design, Reliability Analysis, SERDES, Semiconductors, Signal Integrity, Simulation, Substrate Design, System Integration (SI), Team Player, Technical/Engineering Design
LOCATION
San Jose Bay Area, CA
POSTED
22 days ago

We are seeking a Senior Package Design Engineer to join our custom SOC/ASIC development client. You'll work closely with cross-functional teams in the U.S. and overseas on high-performance package substrate design with a focus on signal/power integrity and routing.

Key Responsibilities:

  • Perform package substrate design and analysis (SI/PI/routing)
  • Collaborate with layout engineers, marketing, and global design teams
  • Use tools like HFSS, ADS for package modeling/simulation
  • Contribute during pre/post-sales processes


Why is This a Great Opportunity

This is an outstanding technology, great opportunity to learn. Growing company with a lot of IP. Everyone contributes.



Qualifications:

  • BS in EE or related field; MS preferred
  • 8–10 years of experience in semiconductor package design
  • Strong SI/PI analysis, modeling, and simulation skills
  • Excellent communication, teamwork, and presentation abilities

 

Preferred Skills:

  • Expertise in high-speed package/PCB design (SerDes, PCIe, LPDDR, Ethernet)
  • Time/frequency domain analysis, impedance, jitter, eye-diagram, BER analysis
  • Experience with Hspice, Redhawk, electro-thermal simulation, PDN modeling
  • Familiarity with reliability analysis and packaging/assembly rules


About the Company

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The PJF Group