Position: Senior Design Engineer
Location: San Jose, CA
LOA: 3 Months+
My client's FPGA Design, CAD andMethodology group is looking for a senior level engineer to develop high speed memory interfaces forveryhigh performance FPGAs. Memory interface types may include existing andupcomingmemory technologies such as DDR3 and DDR4 SDRAM, QDR II+ SRAM, RLDRAM3 and beyond.
Creation of customer presentable IP and documentation.
Coding of designs and algorithms in Verilog and/or C
Complete design cycle of simulation, verification, debug and hardware verification and debug in conjunction with other team members and teams.
Work with field application engineers andcustomer support as needed.
Very strong knowledge of logic fundamentals
Excellentknowledge of Verilog
Capableof writing customer-presentable HDL code and documentation
Knowledgeof high speed timing fundamentals and timing budgets
Good written and oral communications skills
Working knowledge of C; embedded experience with MicroBlaze preferred
Hands-on experience with lab equipment including logic analyzers and high speedoscilloscopes
Workingknowledge of signal integrity methods
5 or more years of related industry experience
Demonstrated ability to work in fast paced and fun multitasking environment
Must have proven record of achieving consistent results
Memory interface and controller experience
Working knowledge of both Windows and UNIX platforms and scripting tools and languages
Background in statistical methods
Good knowledge of verification methodology
System Verilog experience
Please Send Qualified Resumes to: firstname.lastname@example.org