Job Title: Mask Layout Engineer
Location: San Jose, Ca
Start/End Date: 05/26/14
My client is seeking a contractor Mask Design Engineer. The successful candidate will work as part of a team executing projects in advanced 20nm and 16nm CMOS manufacturing processes on state-of-the-art wireline transceiver layout. Project tasks will include: floor-planning; power grid and signal flow planning; advanced transistor level layout; physical and electrical verification
Applicants are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status or sexual orientation. The information requested here is not gathered for employment decisions. It is used only for compliance with Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to 'self-identify', you will not be subject to any adverse treatment.
Skills/Experience: * Strong foundation in layout design for analog/mixed-signal circuits in advanced CMOS processes. * Extensive floorplanning, power grid and signal flow planning experience. * Excellent understanding of signal and clock shielding and isolation techniques. * Excellent understanding of process non-idealities such as STI stress, well proximity effect and design strategies to mitigate these effects. * Experience in the layout of high-speed transceivers, PLLs, receivers, and transmitters * Excellent written and oral communication skills are also required * Minimum education level/experience: Diploma + 10 yrs, BS + 8 yrs.
1. Do you have experience on the process nodes and the block functions? Prefer 20nm process or advanced, and prefer the experience with analog mixed signal field.
2. Will you be able to start no later than June 15th