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Senior Analog IC Design Engineer - PLL

Job Description


A growing company in the Phoenix, Arizona (AZ) area is looking for Sr. Analog Mixed Signal Design Engineers with PLL Design experience including Clocking IC's.

They are looking for candidates nationwide willing to relocate to the Phoenix, AZ area. Our client will provide a relocation package. This Analog Mixed-Signal IC Design Engineering position will provide key contributions to state of the art PLLs for use in high performance clocking IC's, Network and Communication IC's. Responsibilities of the position include product definition, design, layout, lab verification, and releases to production. You will be responsible designing PLL IC's

Job Requirements


  • Candidates must have a BSEE, MSEE or Ph.D. with 5-15+ years of IC design work experience.

  • Extensive high performance PLL design experience is preferred. An excellent track record in CMOS and/or BiCMOS IC design is required.

  • Experience in designing Clocking / PLL IC's such as Programmable Synthesizers and Clock Generators (VersaClock), Real Time Clocks, PC Motherboard Clocks and etc is desired.

  • Related experience in digital PLLs, crystal oscillators, VCXOs, on-chip regulators, DACs, and ADCs are pluses.

  • Understanding of transistor modeling and circuit noise theory is required.

  • Digital design skills would be gladly welcomed, but are not required.

  • Strong communication skills, a strong work ethic, and the ability to work well individually and within a team environment.

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