The successful candidate will be part of a small team of engineers working on

the design of a complex FPGA with an embedded or discrete processor and a large amount of logic/memory/state machines. Candidate will perform analysis, trade-offs and develop hardware requirements documents. Candidate will interface with internal and external customers, present at design reviews requiring good written and verbal communications and presentation skills. Candidate must be a self starter with the ability to prioritize among multiple tasks with minimal supervision.

Minimum of 10 years experience as a contributing member of a complex FPGA or ASIC design team using VHDL or Verilog is required. Understanding of datacom protocols (IPv4, IPv6, Ethernet, etc.) and concepts is required. Experience in VHDL or Verilog, advanced verification techniques and Xilinx/Altera FPGA tool

flow for large FPGAs is required. Experience in the area of IP Packet Processing, high speed data paths as well as storage products is preferred. Experience in ASIC style verification methodology with Telecom type products with System Verilog for verification is a plus. Proven ability to move from FPGA design to

EE board level design utilizing MENTOR or CADENCE tools from conceptualization, board bringup and thru HW/SW integration is a plus. Experience designing with/around 32-bit processors is required. Previous experience with interfaces such as PCI, PCE-e, etc is a plus. Experience in the area of schematic netlist extraction for board level datapath verification integrating multiple FPGAs is desired.
Secret level U.S. DoD security clearance is required.